![]() ![]() For a MOSFET built on the typical (100) surface, channel orientation, the eqi-energy surfaces of the valence band form an unusually shaped surface, with four "wings" and four "feet." When the MOSFET is uniaxially strained, the shear components warp the bands to form an optimal "disk" or "hockey puck" eqi-energy surface. ![]() The way this works for holes is as follows. Lower scattering means better mobility and higher drive current for better performance. In addition, the splitting of the bands reduces scattering. Low effective mass means better mobility and higher drive current for better performance. When the stress values get over ~2 GPa, the majority of the electrons are in the ellipsoids with the lowest effective mass. The electrons move from the high energy "in-plane" ellipsoids (with the poor effective mass) to the low energy "out-of-plane" ellipsoids (with the good effective mass). When the MOSFET is strained, the energy bands split, with the "out-of-plane" ellipsoids having lower energy. For a MOSFET built on the typical (100) surface, channel orientation, the eqi-energy surfaces of the conduction band are oriented with two "out-of-plane" ellipsoids with good (low) effective mass and four "in-plane" ellipsoids with poor (high) effective mass. ![]() The way this works for electrons is as follows. The second is by moving carriers to places with good effective mass (or reducing movement of carriers to places with bad effective mass). The first is by reducing the effective mass of the silicon. Strain provides mobility improvement in two ways. Strain causes the Si atoms to stretch apart by ~1%. Process Strain, Mobility Enhancement and Drive Current The addition of strain in both NMOS and PMOS enhanced the channel mobility, resulting in improved drive current (and improved performance) for both NMOS and PMOS. PMOS strain was introduced by replacing the conventional source/drain region with strained SiGe (a process often called embedded-SiGe or e-SiGe). NMOS strain was introduced by adding a high-stress layer that wrapped around the transistor (a process sometimes named CESL, or contact etch-stop layer after the most common layer used for the stressor). Intel made a significant breakthrough in the 90nm process generation by introducing strained silicon on both the N and PMOS transistors. ![]()
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